The present application relates to semiconductor device fabrication, and more particularly to formation of metal-oxide-semiconductor field effect transistors (MOSFETs) with improved scaling and reduced parasitic capacitance.
In the semiconductor industry, there is a constant demand to increase the operating speed of integrated circuits (ICs). The demand for increased speed, in turn, has resulted in a continual size reduction of the semiconductor devices including field effect transistors (FETs). However, the aggressive scaling or size reduction of the FETs raises various technical issues relating to contact spacing and parasitic capacitance, namely gate-to-source/drain contact capacitance, which need to be addressed in order to meet the requirements for both device performance and manufacturing yield.